Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same

ABSTRACT

The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, and methods for making the same, wherein the metallization structure includes a substrate with a substantially planar upper surface, a foundation metal layer disposed on a portion of the substrate upper surface, a primary conducting metal layer overlying the base metal layer, and a metal spacer on the sidewalls of the primary conducting metal layer and the foundation metal layer. The present invention also provides a metallization structure, and a method for making the same, wherein the metallization structure includes a substrate with a foundation metal layer disposed thereon, a dielectric layer with an aperture therethrough being disposed on the substrate, where the bottom of the aperture exposes the foundation metal layer of the substrate and a metal spacer on the sidewall of the aperture and a line or plug of a primary conducting metal fill the remaining portion of the aperture. These metallization structures are useful for reducing the incidence and severity of thermally-induced stress voids.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to the field of semiconductordevice design and fabrication. Specifically, the invention relates tomethods for manufacturing metallization structures in integrated circuitdevices and the resulting structures.

[0003] 2. State of the Art

[0004] Integrated circuits (ICs) contain numerous individual devices,such as transistors and capacitors, that are interconnected by anintricate network of horizontal and vertical conductive lines commonlytermed interconnects. Exemplary interconnect structures are disclosed inU.S. Pat. Nos. 5,545,590, 5,529,954, 5,300,813, 4,988,423, and5,356,659, each of which patents is hereby incorporated herein byreference.

[0005] Aluminum interconnect structures are decreasing in size and pitch(spacing), as the industry trend continues to, and including, submicronfeatures pitches. The resultant reduction in structure sizes leads tonumerous reliability concerns, including electromigration and stressvoiding of the interconnect structures.

[0006] Stress notches (also known as stress voids) on the surface ofconductive interconnect structures are of concern because the voids ornotches degrade reliability and device performance. Stress notches, whenformed in a conductive line, may render the line substantiallydiscontinuous and unable to effectively transmit a signal. Stressnotches at a grain boundary are extremely detrimental, as they maypropagate along the boundary and sever the conductive line completely.

[0007] Stress notches are also undesirable because they can alter theresistivity of a conductive line and change the speed at which signalsare transmitted. Resistivity changes from stress notching are especiallyimportant as line dimensions shrink, because notching in a submicronconductive line alters resistivity more than notching in a larger linewith its consequently greater cross-sectional area. Thus, the ever morestringent pitch sizing and higher aspect ratios (height to width of thestructure or feature) sought by practitioners in the art have imitatedconsiderable stress voiding concerns.

[0008] It is believed that stress notching results from both structuraland thermal stresses between conductive lines and adjacent insulatingand passivation layers. Kordic et al., Size and Volume Distributions ofThermally Induced Stress Voids in AlCu Metallization, Appl. Phys. Lett.,Vol. 68, No. 8, Feb. 19, 1996, pp. 1060-1062, incorporated herein byreference, describes how stress voids begin at the edge of a conductiveline where the density of the grain boundaries is largest. Asillustrated in FIG. 12 herein, stress notches form at the exteriorsurfaces and surface intersections of the conductive lines in order torelieve areas of high stress concentration. The notches may thenpropagate into, and across, the interior of the conductive line untilthe line becomes disrupted, cracked, and/or discontinuous.

[0009] Aluminum (Al) and Al alloy (such as Al/Cu) lines are especiallysusceptible to stress notching because of both the thermal expansionmismatch between Al and adjacent layers and the relatively low meltingpoint of Al. As the temperature changes, stresses are induced in Al orAl alloy lines because aluminum's coefficient of thermal expansion (CTE)differs from the CTE of the materials comprising the adjacent layers. Torelieve these stresses, Al atoms migrate and form stress notches.Further, because Al has a low melting point, Al atoms migrate easily atlow temperatures and aggravate a tendency toward stress notch formation.

[0010] Several methods have been proposed to reduce stress notching. Oneproposed method uses a material less susceptible to stress notching,such as copper (Cu) or tungsten (W), in the conductive line. Using Cu inconductive lines, however, has in the past resulted in several problems.First, copper is difficult to etch. Second, adhesion between copper andadjacent insulating layers is poor and thus poses reliability concerns.Third, adding Cu to Al lines may reduce stress notching, but beyond acertain Cu concentration, device performance may begin to degrade.Fourth, as conductive line geometries shrink, adding Cu to Al linesseems less effective in reducing stress notching. Finally, even using Cuinterconnects in the manner employed in the prior art can still lead tonotching effects, especially at 0.1 μm geometries and below since, atsuch dimensions, line widths have become so small that any imperfectioncan cause opens. Using W in Al conducting lines is also undesirable—Whas a high resistivity, and therefore reduces signal speed.

[0011] Another proposed method to reduce stress notching modifies howthe layers adjacent conductive lines (e.g., insulating and passivationlayers) are formed. This method has focused, without notable success, onthe rate, temperature, and/or pressure at which the adjacent layers aredeposited, as well as the chemical composition of such layers.

[0012] Yet another proposed method to reduce stress notching comprisesforming a cap on the conductive lines. Such caps can be formed from TiN,W, or Ti-W compounds. These materials have higher melting points than Aland, therefore, have a higher resistance to stress notching. Adisadvantage in using such caps, however, is that additional processsteps, such as masking steps, are required.

[0013] U.S. Pat. No. 5,317,185, incorporated herein by reference,describes still another proposed method for reducing stress notching.This patent discloses a IC device having a plurality of conductivelines, where the outermost conductive line is a stress-reducing line.This stress reducing line is a non active structure which reduces stressconcentrations in the inner conductive lines.

SUMMARY OF THE INVENTION

[0014] The present invention relates to a metallization structure forsemiconductor device interconnects comprising a substrate having asubstantially planar upper surface, a metal layer disposed on a portionof the substrate upper surface, a conducting layer overlying the metallayer, and metal spacers flanking the sidewalls of the conducting layerand the underlying metal layer. The metal layer and metal spacers do notencapsulate the conducting layer. The substrate upper surface ispreferably a dielectric layer. The conducting layer preferably comprisesaluminum or an aluminum-copper alloy, but may also comprise copper. Whenthe conducting layer comprises Al, the metal layer and metal spacerpreferably comprise titanium, such as Ti or TiN. An optional dielectriclayer, preferably silicon oxide, may be disposed on the conductinglayer. When the optional dielectric layer is present, the metal spacerextends along the sidewall of the dielectric layer.

[0015] The present invention also relates to a metallization structurecomprising a substrate having a metal layer disposed thereon, adielectric layer having an aperture therethrough disposed on thesubstrate so the bottom of the aperture exposes the upper surface of themetal layer, at least one metal spacer on the sidewall of the aperture,and a conducting layer filling the remaining portion of the via. Themetal layer and metal spacer preferably comprises titanium, such as Tior TiN. At least one upper metal layer may be disposed on the conductinglayer.

[0016] The present invention further relates to a method for making ametallization structure by forming a substantially planar firstdielectric layer on a substrate, forming a metal layer over the firstdielectric layer, forming a conducting layer over the metal layer,forming a second dielectric layer over the conducting layer, removing aportion of the second dielectric layer, conducting layer, and metallayer to form a multi-layer structure, and forming metal spacers on thesidewalls of the multi-layer structure. The process optionally removesboth the second dielectric layer portion of the multi-layer structureand the laterally adjacent portions of the metal spacers.

[0017] The present invention additionally relates to a method for makinga metallization structure by forming a substrate comprising a metallayer disposed thereon, forming a dielectric layer comprising anaperture on the substrate so the bottom of the aperture exposes theupper surface of the metal layer, forming a metal spacer on the sidewall(in the case of a via) or sidewalls (in the case of a trench) of theaperture, and forming a conducting layer in the remaining portion of thevia. At least one upper metal layer may optionally be formed on theconducting layer.

[0018] The present invention also relates to a method for making ametallization structure by forming a substrate comprising a metal layeron the surface thereof, forming on the substrate a dielectric layercomprising an aperture so the bottom of the aperture exposes the surfaceof the metal layer, forming a conducting layer in the aperture, formingan upper metal layer overlying the dielectric layer and the aperture,removing the portions of the upper metal layer overlying the dielectriclayer, removing the dielectric layer, removing the portions of the metallayer not underlying the aperture to form a multi-layer metal structure,and forming a metal spacer on the sidewall or sidewalls of themulti-layer metal structure.

[0019] The present invention provides several advantages when comparedto the prior art. One advantage is that thermally-induced stress voidsare reduced because the metal layer and metal spacer comprise materialsexhibiting good thermal-voiding avoidance characteristics. Anotheradvantage is that the size of conductive lines can be shrunk further incomparison to dimensions achievable by conventional processes, sinceonly one additional deposition and etch step, without an additionalmasking step, is needed to form the metallization structure. Shrinkingof conductive lines is necessary as device geometries decrease to lessthan 0.1 μm, At these small geometries, even small notches cansignificantly decrease conductivity.

[0020] The invention also specifically includes semiconductor devicesincluding the inventive metallization structures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0021] The present invention, in part, is illustrated by theaccompanying drawings in which:

[0022]FIGS. 1, 2, 3 a, and 3 b illustrate cross-sectional views of oneprocess of forming a metallization structure, and the structure formedthereby, according to the invention;

[0023]FIGS. 4, 5, 6, 7 a, and 7 b illustrate cross-sectional views ofanother process of forming a metallization structure, and the structureformed thereby, according to the invention;

[0024]FIGS. 8 and 9 illustrate cross-sectional views of yet anotherprocess of forming a metallization structure, and the structure formedthereby, according to the invention;

[0025]FIGS. 10 and 11 illustrate cross-sectional views of still anotherprocess of forming a metallization structure, and the structure formedthereby, according to the invention; and

[0026]FIG. 12 illustrates a partial cross-sectional, perspective view ofa conventional, prior art metallization structure exhibiting stressvoids or notches.

DESCRIPTION OF THE INVENTION

[0027] Generally, the present invention relates to a metallizationstructure for interconnects and semiconductor devices including same.Specifically, the present invention reduces stress voiding, especiallythermally-induced stress voiding, in conducting lines. The metallizationstructures described below exemplify the present invention withoutreference to a specific device because the inventive process andstructure can be modified by one of ordinary skill in the art for anydesired device.

[0028] The following description provides specific details, such asmaterial thicknesses and types, in order to provide a thoroughdescription of the present invention. The skilled artisan, however,would understand that the present invention may be practiced withoutemploying these specific details. Indeed, the present invention can bepracticed in conjunction with conventional fabrication techniquesemployed in the industry.

[0029] The process steps described below do not form a complete processflow for manufacturing IC devices. Further, the metallization structuresdescribed below do not form a complete IC device. Only the process stepsand structures necessary to understand the present invention aredescribed below.

[0030] One embodiment of a process and resulting metallization structureof the present invention is illustrated in FIGS. 1, 2, 3 a, and 3 b.This embodiment may be characterized as a predominantly “subtractive”process, in comparison to the second embodiment discussed hereinafter,in that portions of superimposed material layers are removed to definethe interconnect structure features, such as lines. As shown in FIG. 1,a portion of semiconductor device 2 includes substrate 4 with overlyingfirst dielectric layer 6. Substrate 4 may be any surface suitable forintegrated circuit device formation, such as a silicon or othersemiconductor wafer or other substrate, and may be doped and/or includean epitaxial layer. Substrate 4 may also be an intermediate layer in asemiconductor device, such as a metal contact layer or an interleveldielectric layer. Preferably, substrate 4 is a silicon wafer or bulksilicon region, such as a silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS) structure.

[0031] First dielectric layer 6 may comprise any dielectric materialused in IC device fabrication. Examples of such dielectric materialsinclude silicon oxide, silicon nitride, silicon oxynitride, siliconoxide containing dopants such as boron (B) or phosphorus (P), organicdielectrics, or a layered dielectric film of these materials.Preferably, first dielectric layer 6 is silicon oxide orborophosphosilicate glass (BPSG). First dielectric layer 6 may be formedby any process yielding the desired physical and chemicalcharacteristics, such as thermal oxidation, thermal nitridation, orvapor deposition.

[0032] Overlying first dielectric layer 6 is metal layer 8. One or moreindividual metal layers may be used as metal layer 8. For example, iftwo superimposed metal layers are employed (represented by the dashedline in metal layer 8), an adhesion-promoting metal layer can be afirst, lower portion of metal layer 8 on dielectric layer 6 and a stressreducing layer can be a second, upper portion of metal layer 8. Othermetal layers might be included for other functions, such as a layer forreducing electromigration. Preferably, a single metal layer is used asmetal layer 8, especially when the single layer can reduceelectromigration, function as an adhesion promoting layer, and functionas a stress reducing layer. If two metal layers are employed, the first,upper metal layer may, for example, comprise tantalum, titanium,tungsten, TaN, or TiN and the second, lower metal layer overlyingdielectric layer 6 may, for example, comprise TiN, TiW, WN, or TaN.

[0033] Metal layer 8 includes not only metals, but their alloys andcompounds (e.g., nitrides and silicides). For example, a metal layercontaining titanium might also contain nitrogen or silicon, such astitanium nitride or titanium silicide. Any metal, metal alloy, or metalcompound can be employed in metal layer 8, provided it exhibits thecharacteristics described above, either alone or when combined withother metal layers. Examples of metals that can be employed in metallayer 8 include cobalt (Co), Ti, W, Ta, molybdenum (Mo), and alloys andcompounds thereof, such as TiW or TiN. Preferably, metal layer 8comprises titanium. Titanium is a good adhesion layer and serves as astress reducing layer since Ti exhibits good thermal voiding resistancecharacteristics.

[0034] Metal layer 8 is deposited or otherwise formed by any processused in IC device fabrication. For example, metal layer 8 may bedeposited by chemical vapor deposition (CVD) or physical vapordeposition (PVD) techniques, depending on the characteristics requiredof the layer. As used herein, the term “CVD techniques” encompasses,without limitation, plasma-enhanced CVD, or PECVD. Preferably, whenmetal layer 8 is Ti, this layer is formed by sputtering (a form of PVD)a film of Ti. If metal layer 8 is a metal nitride, it may be formed, forexample, by depositing the metal in a nitrogen-containing atmosphere orby depositing the metal and annealing in a nitrogen-containingatmosphere. If metal layer 8 is a metal silicide, it may be formed, forexample, by first depositing either the metal layer or a silicon layer,then depositing the other, and heating to react the two layers and formthe silicide. If metal layer 8 is a metal alloy, it may be formed by anyprocess suitable for depositing the metal alloy. For example, eithersputtering or CVD techniques can be employed.

[0035] Conducting layer 10 is then formed over metal layer 8. Conductinglayer 10 may comprise any conducting material used in IC devicefabrication. Preferably, conducting layer 10 comprises a conductingmetal, such as Al, optionally containing other elements such as Si, W,Ti, and/or Cu. More preferably, conducting layer 10 is analuminum-copper alloy. Conducting layer 10 may also be formed of Cu.Conducting layer 10 may be formed by any method used in IC devicefabrication such as CVD or PVD techniques. Preferably, conducting layer10 is deposited by a PVD method such as sputtering, as known in the art.Second dielectric layer 12 is next deposited or otherwise formed on topof conducting layer 10. Second dielectric layer 12 comprises anydielectric material used in IC device fabrication, including thoselisted above. Preferably, second dielectric layer 12 comprises amaterial that serves as an etch stop, as explained below. Morepreferably, dielectric layer 12 comprises fluorine-doped silicon oxideor other low dielectric constant material. Second dielectric layer 12may be formed by any suitable process giving the desired physical andchemical characteristics, such as CVD, PECVD (plasma enhanced chemicalvapor deposition, spin-on methods, or otherwise, depending upon thedielectric material selected. For use of the preferred fluorine-dopedsilicon oxide, the preferred deposition method is PECVD.

[0036] As shown in FIG. 2, a portion of second dielectric layer 12,conducting layer 10, and metal layer 8 have been removed, formingmulti-layer structure 13. The portions of layers 8, 10 and 12 areremoved by any IC device fabrication process, such as aphotolithographic patterning and dry etching process. The resultingmulti-layer structure forms the basis for an interconnect structureaccording to the present invention. Of course, the patterning and etchprocess would normally be performed to define a large number ofinterconnect structures, such as conductive lines 100 (see FIGS. 3a and3 b) extending across substrate 4.

[0037] As also shown in FIG. 2, second metal layer 14 (also termed ametal spacer layer) is then deposited on first dielectric layer 6 andover multi-layer structure 13. In similar fashion to the structure ofmetal layer 8, one or more individual metal layers, illustrated by thedashed line within metal layer 14, may be used as metal layer 14.Preferably, a single metal layer is used as metal layer 14 for the samereasons as those set forth for metal layer 8.

[0038] Like metal layer 8, metal layer 14 includes not only metals, buttheir alloys and compounds (e.g., nitrides and silicides). Preferably,when conducting layer 12 comprises aluminum, metal layer 14 comprisesTi. If conducting layer 10 comprises Cu, metal layer 14 preferablycomprises TiW. More preferably, metal layer 14 comprises the same metalas first metal layer 8. Metal layer 14 may be deposited or otherwiseformed by a process similar to the process used to form metal layer 8.Preferably, metal layer 14 is formed by a conformal deposition process,such as CVD.

[0039] Next, as illustrated in FIG. 3a, metal layer 14 is spacer etchedto remove portions of the metal layer 14 on first dielectric layer 6 andthe second dielectric layer 12, thereby leaving spacers 16 on themulti-layer structure 13. A spacer etch is a directional sputtering etchwhich removes metal layer 14 so that spacers 16 remain on the sidewallsof multi-layer structure 13. The spacer etch uses the first and seconddielectric layers as an etch stop.

[0040] If desired, second dielectric layer 12 can then be removed.Second dielectric layer 12 can be removed by any process which removesthe second dielectric layer without removing first dielectric layer 6.If the first and second dielectric layers comprise different materials(e.g., when second dielectric layer 12 is silicon oxide and the firstdielectric layer 6 is BPSG), any process which selectively etches thesecond dielectric layer 12 can be employed. The etch process would alsoremove the portions of sidewalls 16 laterally adjacent dielectric layer12, thus resulting in the metallization structure illustrated in FIG.3b. When the first and second dielectric layers are similar or havesimilar etch rates, (e.g., when both are silicon oxide orfluorine-doped), a facet etch process can be used. As shown in brokenlines in FIG. 3b, when the first and second dielectric layers 6 and 12exhibit similar etch rates, the thickness of layer 6 will be reduced bysubstantially the thickness of removed layer 12.

[0041] The metallization structures illustrated in FIGS. 3a and 3 breduce thermally-induced stress voids in conductive lines 100. Metallayer 8 and metal spacers 16 serve as a protective coating at therespective lower and lateral surfaces of conductive lines 100 and atintersections thereof, thereby reducing the incidence of stress voids bypreventing them from starting at these surfaces and intersectionsthereof on conductive line 100. Metal layer 8 and metal spacers 16 alsoincrease reliability of conductive line 10 without reducing itsresistance.

[0042] The metallization structures of FIGS. 3a and 3 b can then beprocessed as desired to complete the IC device. For example, aninterlevel dielectric layer could be deposited thereover, contact or viaholes could be cut in the interlevel dielectric, a patterned metal layercould be formed to achieve a desired electrical interconnection pattern,and a protective dielectric overcoat deposited and patterned to exposedesired bond pads.

[0043] Another embodiment of a process and resulting metallizationstructures of the present invention is represented in FIGS. 4 through11. This embodiment may be characterized as more of an “additive” methodor process than that described with respect to FIGS. 1 through 3, inthat metallization structures for interconnects are formed by depositionin apertures, such as vias or trenches. As such, it should be noted thatcusping of material deposited to line the sidewall or sidewalls of anaperture may be of concern if the method of deposition is notsufficiently anisotropic or, in some instances, the aperture exhibits avery high aspect ratio. In FIG. 4, metal layer 52 has been deposited orotherwise formed over substrate 50. Any of the substrates employable assubstrate 4 above can be used as substrate 50. Preferably, substrate 50is a silicon wafer or bulk silicon region, such as an SOI or SOSstructure. Such substrate 50 can have active and passive devices andother electrical circuitry fabricated on it, these circuit structuresbeing interconnected by the metallization structures of the presentinvention. Therefore, a direct electrical path may exist between thedevices and circuitry of the substrate 50 (or 4), the devices andcircuitry being omitted herein for simplicity.

[0044] Metal layer 52 may comprise a discrete conductive member, such asa wire, a stud, or a contact. Preferably, metal layer 52 issubstantially similar to metal layer 8 described above and may be of anyof the same metals, alloys or compounds. If desired, a dielectric layer51 can be formed on substrate 50 and beneath metal layer 52. Dielectriclayer 51 is substantially similar to dielectric layer 6 described above.

[0045] As illustrated in FIG. 4, dielectric layer 54 is then depositedor otherwise formed on metal layer 52. Dielectric layer 54 may be anydielectric or insulating material used in IC device fabrication, such assuch as those listed above for dielectric layer 12. Preferably,dielectric layer 54 is silicon oxide or spin on glass (SOG). Dielectriclayer 54 may be formed by any IC device fabrication process giving thedesired physical and chemical characteristics.

[0046] An aperture such as a via or trench 56 is then formed indielectric layer 54 by removing a portion of dielectric layer 54 toexpose underlying metal layer 52. Aperture 56 may be formed by any ICdevice manufacturing method, such as a photolithographic patterning andetching process.

[0047] As shown in FIG. 5, metal collar 60 is formed on the sidewalls ofaperture 56, using a spacer etch as known in the art. It will beunderstood that the term “collar” encompasses a co-parallel spacerstructure 60 if aperture 56 is a trench extending over substrate 50.Similar to metal layer 14, collar 60 may contain one or more metallayers with a single metal layer preferably used. Also in similarfashion to metal layer 14, collar 60 may include not only metals, buttheir alloys and compounds. Like metal layer 14, any metal can beemployed in collar 60, provided it exhibits the desired characteristics,either alone or when combined with other metal layers, and the metalsapplicable to metal layer 14 are equally applicable to collar 60.Preferably, collar 60 comprises the same metal as conducting layer 52.More preferably, when conductive layer 52 comprises Al, collar 60comprises Ti.

[0048] Collar 60 is formed by an IC device fabrication process whichdoes not degrade metal layer 52, yet forms a collar or spacer-likestructures 60 on the sidewall or sidewalls of aperture 56. For example,layer 61 (shown in FIG. 4) of a material from which collar 60 is formedcan be conformally deposited on dielectric layer 54 and the walls of via56. Conformal coverage yields a substantially vertical sidewall in thedielectric aperture. While not preferred, a partially conformal layer ofthe material can be deposited instead. A highly conformal process ispreferably employed to form layer 61. Portions of layer 61 on the bottomof via 56 and top of dielectric layer 54 are then removed, preferably byusing an appropriate directional etch, such as reactive ion etching(RIE).

[0049] Conducting layer 62 is next deposited or otherwise formed to fillaperture 56 and extend over dielectric layer 54, as shown in brokenlines in FIG. 5. Conducting layer 62 may be deposited by any IC devicefabrication method yielding the desired characteristics. For example,conducting layer 62 may be deposited by a conformal or non-conformaldeposition process. An abrasive planarization process, such aschemical-mechanical planarization (CMP), is then used to remove portionsabove the horizontal plane of the upper surface of dielectric layer 54and leave conductive plug (in a via 56) or line (in a trench 56) 64 asillustrated in FIG. 6.

[0050] Similar to conducting layer 10, conducting layer 62 comprises anyconducting material used in IC devices. Preferably, conducting layer 62comprises aluminum, optionally containing other metals such as Si, W,Ti, and/or Cu. More preferably, conducting layer 62 is analuminum-copper alloy. Conducting layer 62 may also comprise coppermetal.

[0051] Dielectric layer 54 can then be optionally removed, thus formingthe interconnect structure represented in FIG. 7a. Dielectric layer 54can be removed by any process which does not degrade any of metal layer52, conductive layer 62, or collar 60. For example, when dielectriclayer 54 is silicon oxide, it may be removed by an HF wet etch solutionor an oxide dry etch process. If desired, portions of metal layer 52 canthen be removed, preferably by a directional etching process, to obtainthe interconnect structure shown in FIG. 7b.

[0052] In an alternative method, upper metal layer 66 can be formed overconductive plug or line 64 as depicted in FIG. 8. Like metal layer 52,upper metal layer 66 may contain one or more individual metal layers.Preferably, a single metal layer is used as upper metal layer 66.Similar to metal layer 52, upper metal layer 66 may contain not onlymetals, but their alloys and compounds. Preferably, metal layer 66comprises the same material as collar 60. More preferably, whenconductive plug 64 comprises Al, metal layer 66 comprises Ti.

[0053] Upper metal layer 66 can be formed over conductive plug 64 in thefollowing manner. Conductive layer 62 is deposited in aperture 56 andover dielectric layer 54 as described above with respect to FIG. 5.Prior to completely filling aperture 56, however, the deposition ofconductive layer 62 is halted as shown at 62 a in FIG. 5, leaving anupper portion of aperture 56 empty (i.e, a recess is left at the top ofaperture 56). Upper metal layer 66 is then deposited over conductivelayer 62, including the still-empty upper portion of aperture 56.Portions of conductive layer 62 and upper metal layer 66 above thehorizontal plane of dielectric layer 54 are then removed by aplanarization process, such as CMP, to form a completely enveloped, orclad, interconnect structure. If desired, portions of dielectric layer54 and metal layer 52 flanking the interconnect structure can be removedas described above to form the structure of FIG. 9.

[0054] In another process, variant after forming metal layer 52 onsubstrate 50 and forming dielectric layer 54 with aperture 56therethrough, but prior to forming collar 60, conductive plug or line 64could be formed in aperture 56 as described above. Upper metal layer 66could then be deposited, as described above, over conductive plug orline 64 and dielectric layer 54 to obtain the structure illustrated inFIG. 10. Portions of upper metal layer 66 not overlying conductive plugor line 64 could then be removed by a photolithographic pattern and etchprocess, followed by removing dielectric layer 54 by the methoddescribed above, to obtain the structure illustrated in FIG. 11. Asexplained above, the structure of FIG. 11 could then have a conformedmetal layer deposited and etched (similar to the deposition and etch ofmetal layer 14 above) to form a structure similar to that depicted inFIG. 3a.

[0055] While the preferred embodiments of the present invention havebeen described above, the invention defined by the appended claims isnot to be limited by particular details set forth in the abovedescription, as many apparent variations thereof are possible withoutdeparting from the spirit or scope thereof.

What is claimed is:
 1. A metallization structure for a semiconductordevice, comprising: a substrate comprising a substantially planar uppersurface; a metal layer defining a pattern on a portion of the substrateupper surface; a conducting layer overlying and substantiallycoextensive with the metal layer, said metal layer and said conductinglayer having substantially aligned sidewalls; and metal spacers flankingthe sidewalls of the conducting layer and metal layer.
 2. Themetallization structure of claim 1, further comprising a dielectriclayer on the substrate upper surface and underlying the metal layer. 3.The metallization structure of claim 2, wherein the dielectric layer issilicon oxide or BPSG.
 4. The metallization structure of claim 1,wherein the metal layer is a first metal layer comprising Ti, Ta, W, Coor Mo or alloys or compounds thereof, including TaN or TiN.
 5. Themetallization structure of claim 4, further including a second metallayer disposed between the first metal layer and the substrate andcomprising TiN, TiW, WN, or TaN.
 6. The metallization structure of claim5, wherein the first metal layer comprises titanium or titanium nitride.7. The metallization structure of claim 1, wherein the metal layer istitanium or titanium nitride.
 8. The metallization structure of claim 1,wherein the conducting layer is selected from the group comprisingaluminum and copper.
 9. The metallization structure of claim 8, whereinthe conducting layer is an aluminum-copper alloy.
 10. The metallizationstructure of claim 1, wherein the metal spacers comprise at least onelayer of Ti, Ta, W, Co or Mo, or alloys thereof or compounds thereof,including TaN and TiN.
 11. The metallization structure of claim 11,wherein the metals spacers are titanium or titanium nitride.
 12. Themetallization structure of claim 1, further comprising a dielectriclayer on the conducting layer and having sidewalls aligned therewith,the metal spacers extending along the sidewalls of the dielectric layer.13. The metallization structure of claim 12, wherein the dielectriclayer comprises a low dielectric constant material.
 14. Themetallization structure of claim 13, wherein the dielectric layer isfluorine-doped silicon oxide.
 15. The metallization structure of claim1, wherein the metal layer and the metal spacers comprise the samemetal.
 16. A metallization structure for a semiconductor device,comprising: a substrate having a metal layer disposed thereon; adielectric layer having an aperture therethrough defined by at least onesidewall and exposing the metal layer; a metal spacer on the at leastone sidewall of the aperture; and a conductive layer substantiallyfilling a remaining portion of the aperture.
 17. The metallizationstructure of claim 16, wherein the metal layer comprises tantalum,titanium, tungsten, cobalt, molybdenum, or an alloy or a compound of anythereof, including TaN and TiN.
 18. The metallization structure of claim17, wherein the metal layer is titanium or titanium nitride.
 19. Themetallization structure of claim 16, wherein the at least one metalspacer includes at least one layer of metal comprising tantalum,titanium, tungsten, cobalt, molybdenum, or alloys or compounds thereof,including TaN and TiN.
 20. The metallization structure of claim 19,wherein the at least one metal spacer is titanium or titanium nitride.21. The metallization structure of claim 16, wherein the substratecomprises a dielectric layer underlying the metal layer.
 22. Themetallization structure of claim 21, wherein the dielectric underlyingthe metal layer is silicon oxide or BPSG.
 23. The metallizationstructure of claim 16, wherein the metal layer and the at least onemetal spacer comprise the same metal.
 24. The metallization structure ofclaim 16, wherein the metal layer is a first metal layer comprising Ti,Ta, W, Co or Mo or an alloy or a compound of any thereof, including TaNor TiN.
 25. The metallization structure of claim 24, further including asecond metal layer disposed between the first metal layer and thesubstrate and comprising TiN, TiW, WNV, or TaN.
 26. The metallizationstructure of claim 16, further comprising at least one upper metal layeron the conductive layer and comprising Ti, Ta, W, Co or Mo or an alloyor a compound of any thereof, including TaN or TiN.
 27. Themetallization structure of claim 26, wherein the at least one uppermetal layer comprises a plurality of upper metal layers.
 28. Themetallization structure of claim 16, wherein the at least one uppermetal layer comprises titanium or titanium nitride.
 29. A method formaking a metallization structure for a semiconductor device, comprising:forming a substantially planar first dielectric layer on a substrate;forming at least one metal layer over the first dielectric layer;forming a conducting layer over the metal layer; forming a seconddielectric layer over the conducting layer; removing aligned portions ofthe second dielectric layer, conducting layer, and metal layer to form amulti-layer structure; and forming metal spacers on sidewalls of themulti-layer structure.
 30. The method of claim 29, wherein forming thefirst dielectric layer comprises forming a silicon oxide or BPSG layer.31. The method of claim 29, further including forming the at least onemetal layer of Ti, Ta, W, Co or Mo or an alloy or a compound of anythereof, including TaN or TiN.
 32. The method of claim 31 furtherincluding forming a second metal layer between the first metal layer andthe substrate and comprising TiN, TiW, WN, or TaN.
 33. The method ofclaim 29, further including forming the at least one metal layer oftitanium or titanium nitride.
 34. The method of claim 29, wherein the atleast one metal layer is a single metal layer and further comprisingforming the single metal layer of titanium or titanium nitride.
 35. Themethod of claim 29, further comprising forming the conducting layer fromthe group comprising aluminum and copper.
 36. The method of claim 35,further including forming the conducting layer of an aluminum-copperalloy.
 37. The method of claim 29, further including forming the metalspacers of at least one layer of Ti, Ta, W, Co or Mo, or alloys thereofor compounds thereof, including TaN and TiN.
 38. The method of claim 37,further including forming the metal spacers of titanium or titaniumnitride.
 39. The method of claim 29, further comprising forming adielectric layer on the conducting layer to have sidewalls aligned withthe conductive layer sidewalls, and forming the metal spacers to extendalong the sidewalls of the dielectric layer.
 40. The method of claim 39,further comprising forming the dielectric layer of a low dielectricconstant material.
 41. The method of claim 40, further comprisingforming the dielectric layer of a fluorine-doped silicon oxide.
 42. Themethod of claim 29, further comprising forming the at least one metallayer and the metal spacers of the same metal.
 43. The method of claim29, further comprising forming the at least one metal layer by vapordeposition.
 44. The method of claim 42, further comprising forming theat least one metal layer by CVD, PVD or PBCVD.
 45. The method of claim29, further comprising forming the conducting layer by vapor deposition.46. The method of claim 45, further comprising forming the conductinglayer by CVD, PVD or PECVD.
 47. The method of claim 29, furthercomprising forming the metal spacers by vapor deposition and directionaletching.
 48. The method of claim 47, further comprising effecting thevapor deposition as CVD, PVD or PECVD.
 49. The method of claim 29,wherein removing aligned portions of the second dielectric layer,conducting layer, and metal layer to form a multi-layer structure iseffected by patterning and etching the second dielectric layer, theconducting layer, and the metal layer.
 50. The method of claim 29,further comprising forming the metal spacers by forming a metal spacerlayer over the multi-layer structure and first dielectric layer andremoving portions thereof overlying the first and second dielectriclayers.
 51. The method of claim 50, further comprising forming the metalspacer layer over the multi-layer structure and first dielectric layerby a conformal deposition process.
 52. The method of claim 51, whereinthe portions of the metal layer over the multi-layer structure and firstdielectric layer are removed by etching.
 53. The method of claim 29,further comprising: removing any remaining portion of the seconddielectric layer and upper portions of the metal spacers laterallyadjacent thereto.
 54. The method of claim 53, further comprisingremoving any remaining portion of the second dielectric layer and upperportions of the metal spaces by etching.
 55. A method for making ametallization structure comprising: forming a substrate comprising atleast one metal layer on the surface thereof, forming a dielectric layerover at least one the metal layer; forming an aperture having at leastone sidewall through the dielectric layer to expose a surface of the atleast one metal layer; forming a metal spacer on the at least onesidewall of the aperture; and forming a conductive layer in a remainingportion of the aperture.
 56. The method of claim 55, further comprisingforming the dielectric layer of silicon oxide.
 57. The method of claim55, further including forming the at least one metal layer of Ti, Ta, W,Co or Mo or alloys or compounds thereof, including TaN or TiN.
 58. Themethod of claim 57, wherein the at least one metal layer comprises afirst metal layer, and further including forming a second metal layerbetween the first metal layer and the substrate and comprising TiN, TiW,WN, or TaN.
 59. The method of claim 55, further including forming the atleast one metal layer of titanium or titanium nitride.
 60. The method ofclaim 55, further comprising forming the at least one metal layer byvapor deposition.
 61. The method of claim 60, further comprising formingthe at least one metal layer by CVD, PVD or PECVD.
 62. The method ofclaim 55, further comprising forming the conducting layer by vapordeposition.
 63. The method of claim 62, further comprising forming theconducting layer by CVD, PVD or PECVD.
 64. The method of claim 55,further comprising forming the at least one metal layer and the metalspacer of the same metal.
 65. The method of claim 55, further comprisingforming the metal spacer by vapor deposition and directional etching.66. The method of claim 55, further including forming the metal spacerof at least one layer of Ti, Ta, W, Co or Mo, or alloys or compoundsthereof, including TaN or TiN.
 67. The method of claim 66, furtherincluding forming the metal spacer of titanium or titanium nitride. 68.The method of claim 55, further comprising forming at least one uppermetal layer on the conductive layer.
 69. The method of claim 68, furthercomprising forming the at least one upper metal layer on the conductivelayer from Ti, Ta, W, Co or Mo or alloys or compounds thereof, includingTaN or TiN.
 70. The method of claim 68, further comprising forming theat least one upper metal layer as a plurality of upper metal layers. 71.The method of claim 68, further comprising forming the at least oneupper metal layer of titanium or titanium nitride.
 72. The method ofclaim 68, further comprising forming the at least one upper metal layerby vapor deposition.
 73. The method of claim 72, wherein the vapordeposition is effected by CVD, PVD or PECVD.
 74. The method of claim 55,further comprising removing the dielectric layer and portions of the atleast one metal layer not underlying the aperture.
 75. The method ofclaim 74, further comprising removing the dielectric layer by using ahydrofluoric acid wet etch solution or an oxide dry etch process. 76.The method of claim 74, further comprising removing the portions of theat least one metal layer by directional etching.
 77. A method for makinga metallization structure comprising: forming a substrate comprising atleast one metal layer on the surface thereof; forming a dielectric layerover the at least one metal layer; forming an aperture through thedielectric layer to expose a surface of the at least one metal layer;forming a conducting layer in the aperture; forming at least one uppermetal layer overlying the dielectric layer and the conducting layer inthe aperture; removing portions of the at least one upper metal layeroverlying the dielectric layer, removing the dielectric layer, andremoving portions of the at least one metal layer surrounding theconducting layer to form a multi-layer metal structure having at leastone sidewall; and forming a metal spacer on the at least one sidewall ofthe multi-layer metal structure.
 78. The method of claim 77, furthercomprising forming the dielectric layer of silicon oxide.
 79. The methodof claim 77, further including forming the at least one metal layer ofTi, Ta, W, Co or Mo or alloys or compounds thereof, including TaN orTiN.
 80. The method of claim 79, wherein the at least one metal layercomprises a first metal layer, and further including forming a secondmetal layer between the first metal layer and the substrate andcomprising TiN, TiW, WN, or TaN.
 81. The method of claim 77, furtherincluding forming the at least one metal layer of titanium or titaniumnitride.
 82. The method of claim 77, further comprising forming the atleast one metal layer by vapor deposition.
 83. The method of claim 82,further comprising forming the at least one metal layer by CVD, PVD orPECVD.
 84. The method of claim 77, further comprising forming theconducting layer by vapor deposition.
 85. The method of claim 84,further comprising forming the conducting layer by CVD, PVD or PECVD.86. The method of claim 77, further comprising forming the at least onemetal layer and the metal spacer of the same metal.
 87. The method ofclaim 77, further comprising forming the metal spacer by vapordeposition of a metal layer over the multi-layer metal structure anddirectional etching of the vapor-deposited metal layer.
 88. The methodof claim 77, further including forming the metal spacer of at least onelayer of Ti, Ta, W, Co or Mo, or alloys thereof or compounds thereof,including TaN or TiN.
 89. The method of claim 88, further includingforming the metal spacer of titanium or titanium nitride.
 90. The methodof claim 77, further comprising forming the at least one upper metallayer on the conducting layer from Ti, Ta, W, Co or Mo or an alloy or acompound of any thereof, including TaN or TiN.
 91. The method of claim90, further comprising forming the at least one upper metal layer as aplurality of upper metal layers.
 92. The method of claim 77, furthercomprising forming the at least one upper metal layer of titanium ortitanium nitride.
 93. The method of claim 77, further comprising formingthe at least one upper metal layer by vapor deposition.
 94. The methodof claim 93, wherein the vapor deposition is effected by CVD, PVD orPECVD.
 95. The method of claim 77, further comprising removing thedielectric layer by using a hydrofluoric acid wet etch solution or anoxide dry etch process.
 96. The method of claim 77, further comprisingremoving the portions of the at least one metal layer by directionaletching.
 97. The method of claim 77, further comprising forming theconducting layer from at least one of aluminum and copper.
 98. Themethod of claim 77, comprising forming the metal layer, metal spacer,and upper metal layer of the same metal.
 99. The method of claim 98,wherein the metal is Ti.